In the related art, as illustrated in FIG. 1, a semiconductor device 100 includes an internal circuit 130 and an annular moisture-resistant ring 120 surrounding the internal circuit 130. The moisture-resistant ring 120 is formed continuously around the internal circuit 130 so as to prevent moisture from entering the internal circuit from the outside of the semiconductor device 100.
The semiconductor device 100 is formed by laminating an insulating layer and a wiring layer on a semiconductor substrate. The internal circuit 130 includes a circuit element formed on the semiconductor substrate, a plug portion formed in the insulating layer, and a wiring portion formed in the wiring layer. In the same manner, the moisture-resistant ring 120 includes a plug portion formed in the insulating layer and a wiring portion formed in the wiring layer. The moisture-resistant ring 120 has a structure in which the plug portions and the wiring portions are laminated alternately on the semiconductor substrate. In this manner, the moisture-resistant ring 120 is formed continuously around the internal circuit 130 and forms a wall for preventing the entry of moisture in the direction of the depth on the semiconductor substrate.
Japanese Laid-open Patent Publication No. 1993-136020 discusses auxiliary patterns including respective pairs of the wiring patterns passing through the divided line of the wiring patterns of the semiconductor device. Japanese Laid-open Patent Publication No. 2008-27934 discusses a first moisture-resistant ring surrounding the plurality of semiconductor chips individually and a second moisture-resistant ring surrounding the plurality of semiconductor chips entirely.